The present invention is directed to an apparatus for use with a local computing system for controlling access to a local computing system. The local computing system includes a local processing unit and a local buffer unit operatively connected by a local internal system bus. The local buffer unit controls communications access between an expansion bus and the local internal system bus. The expansion bus is external of both the local computing system and the host computing system. The host computing system includes a host processing unit and a host buffer unit operatively connected by a host internal system bus. Specifically, the present invention is directed to an apparatus commonly known as a bus master circuit used in controlling access by a local computing system to an internal system bus associated with a host computing system.
Of particular interest in connection with the present invention is the structure of the bus master circuit as an integral part of a computer processing unit which may be utilized either as a host computer processing unit (requiring no bus master capability) or as a local computer processing unit (requiring a bus master capability). The mode in which the particular processing unit is employed is determined by setting bits in a register to enable or disable the bus master support circuit portion of the processing unit architecture.
By such incorporation of a bus master support circuit integrally within the design of a computer processing unit, the costs of integration already incorporated for design and manufacture of the computer processing unit are spread across additional applications for which the unit may be utilized. That is, the marginal increase in design and integration cost to incorporate the bus master support circuit of the present invention is minimal in comparison with similar design and integration costs which would be incurred for a wholly separate bus master support circuit.
Further, by employing an integrated system design approach, a computer processing unit configured to operate as a bus master local processing unit has additional intelligent processing capability not generally found nor economically designed into prior art bus master circuits.